LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_SIGNED.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; USE work.PackProj.All; ENTITY Sequenceur IS GENERIC ( NbBits : INTEGER; Tseq : TIME ); PORT ( AdresseSuiv : IN Std_Logic_Vector(NbBits -1 DOWNTO 0) ; Saut : IN Std_Logic ; Clock : IN Std_Logic ; Reset : IN Std_Logic ; ValeurPC : OUT Std_Logic_Vector(NbBits -1 DOWNTO 0) ); END Sequenceur; ARCHITECTURE Flot OF Sequenceur IS BEGIN process variable PC : Std_Logic_Vector(NbBits -1 DOWNTO 0) := (OTHERS => '0'); begin if reset = '1' then PC := (OTHERS =>'0'); else if clock'event and clock ='1' then if Saut = '1' then PC := AdresseSuiv ; else PC := CONV_STD_LOGIC_VECTOR(CONV_POSITIF(PC) + 1, NbBits); end if; end if; end if; ValeurPC <= PC after Tseq; wait on clock, reset; end process; END Flot;