LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_SIGNED.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; ENTITY Additionneur IS GENERIC (Tadd : TIME ; NbBits : INTEGER ); PORT (entree1 : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; entree2 : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; sortie : OUT Std_Logic_Vector(NbBits-1 DOWNTO 0) ) ; END Additionneur ; ARCHITECTURE comportementale OF Additionneur IS BEGIN sortie <= CONV_STD_LOGIC_VECTOR( CONV_INTEGER(entree1) + CONV_INTEGER(entree2), NbBits) AFTER Tadd ; END comportementale ;